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SI9102
Vishay Siliconix
3-W High-Voltage Switchmode Regulator
FEATURES
* 10- to 120-V Input Range * Current-Mode Control * On-chip 200-V, 7- MOSFET Switch * SHUTDOWN and RESET * High Efficiency Operation (> 80%) * Internal Start-Up Circuit * Internal Oscillator (1 MHz)
DESCRIPTION
The SI9102 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc-todc converter up to 3 watts. It can either be operated from a low-voltage dc supply, or directly from a 10- to 120-V unregulated dc power source. This device may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward). The SI9102 is available in 14-pin plastic DIP and 20-pin PLCC packages, and is specified over the D suffix (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
Note: Figures in parenthesis represent pin numbers for 20-pin package.
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S-60752--Rev. F, 05-Apr-99 1
SI9102
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 V VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V ID (Peak) (Note: 300 s pulse, 2% duty cycle) . . . . . . . . . . . . . . . 2 A ID (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 mA Logic Inputs (RESET, SHUTDOWN, OSC IN) . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SOURCE) . . . . . . . . . . . . . . -0.3 V to 7 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . .3 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b. . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 20-Pin PLCC (N Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 mW Thermal Impedance (JA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167C/W 20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/C above 25C c. Derate 11.2 mW/C above 25C
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 V to 13.5 V ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 k to 1 M Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 7 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 120 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k
Tempb
Mind
Typc
Maxd
Unit
VR ZOUT ISREF TREF
OSC IN = - VIN (OSC Disabled) RL = 10 M
Room Full Room
3.92 3.86 15 70
4.0 30 100 0.5
4.08 4.14 45 130 1.0
V k A mV/C
VREF = -VIN
Room Full
Oscillator
Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficient
e
fMAX fOSC f/f TOSC
ROSC = 0 ROSC = 330 kg ROSC = 150 kg f/f = f(13.5 V) - f(9.5 V)/f(9.5 V)
Room Room Room Room Full
1 80 160
3 100 200 10 200 120 240 15 500
MHz kHz % ppm/C
Error Amplifier
Feedback Input Voltage Input BIAS Current Open Loop Voltage Gaine
VFB IFB AVOL BW ZOUT IOUT VOS IOUT
FB Tied to COMP OSC IN = - VIN (OSC Disabled)
Room Room
3.96
4.00 25
4.04 500
V nA dB MHz
Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Input OFFSET Voltage Output Current
OSC IN = - VIN, VFB = 4 V, OSC IN = - VIN (OSC Disabled)
Room Room Room
60 0.7
80 1 1000 -2.0 15 2000 -1.4 40
mA mV mA
Source (VFB = 3.4 V) OSC IN = - VIN (OSC Disabled) Sink (VFB = 4.5 V)
Room Room Room 0.12
0.15
S-60752--Rev. F, 05-Apr-99 2
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SI9102
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Error Amplifier
Power Supply Rejection
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k
Tempb
Mind
Typc
Maxd
Unit
PSRR
9.5 V VCC 13.5 V RL = 100 from DRAIN to VCC VFB = 0 V RL = 100 from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1. IIN = 10 A VCC 10 V Pulse Width 300 s, VCC = 7 V IPRE-REGULATOR = 10 A RL = 100 from DRAIN to VCC See Detailed Description
Room
50
70
dB
Current Limit
Threshold Voltage Delay to Outpute
VSOURCE td
Room Room
1.0
1.2 100
1.4 200
V ns
Pre-Regulator/Start-Up
Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG - VUVLO
+VIN +IIN ISTART VREG VUVLO VDELTA
Room Room Room Room Room Room 8 7.8 7.0 0.3 15 9.4 8.8 0.6
120 10
V A mA
9.7 9.2 V
Supply
Supply Current Bias Current
ICC IBIAS
Room Room
0.45 10
0.6 15
1.0 20
mA A
Logic
SHUTDOWN Delaye SHUTDOWN Pulse RESET Pulse Widthe
tSD tSW tRW tLW VIL VIH IIH IIL
VSOURCE = -VIN, See Figure 2.
Room Room 50 50 25
50
100 ns
Widthe
See Figure 3.
Room Room Room Room
Latching Pulse Width SHUTDOWN and RESET Low Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low
2.0 V 8.0 1 -35 -25 5 A
VIN = 10 V VIN = 0 V IDRAIN = 100 A IDRAIN = 100 mA VDRAIN = 100 V
Room Room
MOSFET Switch
Breakdown Voltage Drain-Source On Resistancef
VBR(DSS) rDS(on) IDSS CDS OPTION FLOWCHART for
Full Room Room Room
200
220 7 5 35 10
V A pF
Drain Off Leakage Current Drain Capacitance
Notes a. Refer to PROCESS information. additional d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. Temperature coefficient of rDS(on) is 0.75% per C, typical. g. CSTRAY Pin 8 = 5 pF
b. Room = 25C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
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SI9102
Vishay Siliconix
TIMING WAVEFORMS
FIGURE 1.
FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
FIGURE 4.
FIGURE 5.
S-60752--Rev. F, 05-Apr-99 4
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SI9102
Vishay Siliconix
PIN CONFIGURATIONS PIN DESCRIPTION
Pin Function
BIAS +VIN DRAIN SOURCE -VIN VCC OSC OUT OSC IN DISCHARGE VREF SHUTDOWN RESET COMP FB
*Pins 1, 4, 6, 13, 15, and 19 = N/C
14-Pin DIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
20-Pin PLCC*
2 3 5 7 8 9 10 11 12 14 16 17 18 20
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9102 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.4 V. If VCC is not forced to exceed the 9.4-V threshold, then VCC will be regulated to a nominal value of 9.4 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.8-V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the preregulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 9.4-V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48-V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. BIAS To properly set the bias for the SI9102, a 390-k resistor should be tied from BIAS to -VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 A.
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SI9102
Vishay Siliconix
Reference Section The reference section of the SI9102 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9102 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1% of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC in and OSC out pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5-V pulse amplitude and 0.5-s pulse width, typical values would be 100 pF in series with 3 k to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. TABLE 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN
H H L L H L L
RESET
H
Output
Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change)
Output Switch The output switch is a 7- , 200-V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the SI9102 is connected internally to -VIN and is independent of the SOURCE.
APPLICATIONS
S-60752--Rev. F, 05-Apr-99 6
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